Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
Clock signals are used within a PLD to control the timing of events. Each process within a PLD may be clocked by a single distributed clock signal, for example, to provide synchronized processing. In some cases, however, not all processes within a PLD are active at all times. That is, some processes do not require a continuous clock signal. Continuously providing a clock signal to a process that does not require such adds unnecessarily to the power consumption of the PLD. As such, designers typically gate a clock signal coupled to an inactive process to reduce power consumption. The gate circuit is typically formed using logic blocks within the PLD. Such external gating of the clock signal, however, may cause an undesired change in the duty cycle of the clock signal.
In addition, most flip-flops employed within commercially available PLDS are single edge triggered (SET) flip-flops. If dual edge triggered (DET) flip-flops are used, designers employ logic blocks within a PLD to form a DET flip-flop. As is well known in the art, in some instances, a DET flip-flop provides reduced power consumption as compared to an SET flip-flop. In addition to reducing power consumption, DET flip-flops can reduce logic requirements of functions such as data registers and shift registers by approximately 50%. The throughput of certain functions using DET flip-flops may also be higher that an equivalent function using SET flip-flops. In other instances, however, an SET flip-flop provides reduced power consumption over a DET flip-flop.
Accordingly, it would be both desirable and useful to provide a method and apparatus for reducing power consumption in a logic device that overcomes one or more power consumption disadvantages associated with SET and DET flip-flops.